As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...