Morningstar

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center New X100 Series Joins Upgraded X200, X300 and XM IP to Address Growing ...
EDN

RISC-V IP expands AI capabilities at the edge

SiFive’s Intelligence Gen 2 RISC-V IP portfolio combines scalar, vector, and matrix compute to accelerate AI workloads. The Gen 2 lineup includes the new X160 and X180, alongside the upgraded X280, ...
Fox 5 San Diego

Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Hsinchu, Taiwan, Oct. 21, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V ...
VentureBeat

Beyond Von Neumann: Toward a unified deterministic architecture

A cycle-accurate alternative to speculation — unifying scalar, vector and matrix compute In dynamic execution, processors speculate about future instructions, dispatch work out of order and roll back ...
JSTOR Daily

SINGULAR VECTOR AND SINGULAR SUBSPACE DISTRIBUTION FOR THE MATRIX DENOISING MODEL

In this paper, we study the matrix denoising model Y = S + X, where S is a low rank deterministic signal matrix and X is a random noise matrix, and both are M × n. In the scenario that M and n are ...