Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies ...

Japan's Advantest has announced an acceleration of its capacity expansion plans for system-on-chip (SoC) test equipment in response to surging demand driven by artificial intelligence (AI) hardware ...

The most effective way to shorten test times is to test more of the SOC IP (intellectual-property) cores in parallel. However, for best results, the SOC design should anticipate parallel testing, and ...

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...

TOKYO, May 15, 2024 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today announced the newest addition to its portfolio of power supplies for the ...

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...