Nasdaq

Synopsys Announces Software-driven SoC Power Analysis Solution, Enabling 1000X Faster Time-to-Results

ZeBu Power Analyzer extends the ZeBu Server 4 emulation system with novel, multi-threaded power analysis engines supporting RTL and gate-level flows Executes billion-cycle activity profiles on ZeBu ...
EDN

Rail analysis for SoC ASICs

Rail analysis for an ASIC system on chip (SoC) falls into two broad categories, static and dynamic (also known as transient). Static analysis is driven by power consumption for the average situation, ...
Electronic Design

Rail-Signoff Analysis Ensures SoC Power Integrity

More than ever, power integrity is vital in the successful creation of today's system-on-a-chip (SoC) designs. That's because e xcessive rail voltage drop ( IR drop) and ground bounce can create ...
Dark Reading

Cloud Security, PowerShell Expertise Emerge as Key SOC Analyst Skills

Though artificial intelligence is poised to drastically transform enterprise security operations centers (SOCs), for the moment at least, the top three technologies for new hires to be familiar with ...
EDN

Power-grid analysis on SOC-graphics-chip design

Accurate power-grid analysis of 65-nm and smaller chips is becoming increasingly important to ensure reliable operation of devices in the field. Re-spins due to on-chip power-distribution issues are ...
Electronic Design

Signal-Integrity Analysis Tool Leads Way To SoC Timing Closure

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...
Design-Reuse

Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug

San Jose, CA , Nov. 22, 2016 – Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and ...