EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Design-Reuse

Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1

Kaiserslautern, Germany, Oct. 28, 2015 - Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...
Electronic Design

Low-Density Parity Check Error Correction for Solid State Storage

Error Correcting Code (ECC) technology, such as Low-Density Parity Check codes, has been around longer than most of you reading this have been alive. The reason is ...