Semiconductor Engineering

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as ...
Semiconductor Engineering

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of ...
EDN

DRAM MIMCAP process is next focus for IMEC 32-nm project

LONDON — Belgian research organization IMEC has extended its work on 32-nm CMOS device scaling to include a project on DRAM MIMCAP (metal-insulator-metal capacitors) process technology. The group says ...
EDN

DRAM basics and its quest for thermal stability by optimizing peripheral transistors

For decades, compute architectures have relied on dynamic random-access memory (DRAM) as their main memory, providing temporary storage from which processing units retrieve data and program code. The ...